a. Field of the Invention
The present invention generally relates to semiconductor device testing, and more particularly, to the enhancing capacitance-voltage (C-V) characteristic measurements of such semiconductor devices.
b. Background of Invention
Semiconductor device performance may be measured using a myriad of techniques and instruments. For example, in order to perform Atomic Force Probing (AFP) of a semiconductor device or structure, various layers may need to be removed for exposing the device or structure's contacts (e.g., tungsten studs) or surface prior to probing. Such layer removal or delayering may be carried out using either more coarse methods such as chemical mechanical polishing (CMP) or relatively high-precision techniques employing, for example, focused or collimated high-energy (>500 eV) ion beam etching. Such delayering techniques may, however, damage the device or structure's surface, or alternatively, introduce unwanted irregularities (e.g., unwanted ion implantation) into the device or structure. For example, the process used to prepare the device or structure prior to test or evaluation may undesirably introduce defects (e.g., gallium ion implantations due to high energy ion beam etching) or produce shifts in performance characteristics (e.g., MOSFET threshold voltage (Vt) shifts). This may subsequently be misconstrued as a device characteristic resulting from fabrication processes as opposed to a measurement induced defect.
In addition, once the delayering of the structure exposes, for example, a contact, the AC characteristics of the structure under test (e.g., FET device) may be determined. One important AC characteristic that may be used to, among other things, determine doping issues (i.e., concentration, distribution, etc.) is capacitive-voltage (C-V) measurements. However, as device geometries continue to reduce, AC characteristic measurements such as C-V measurements may become more challenging.